The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2013

Filed:

Jan. 07, 2010
Applicant:

Mathias Krauss, Dresden, DE;

Inventor:

Mathias Krauss, Dresden, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type.


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