The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8461892 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 11, 2013

Filed:

Sep. 25, 2012
Applicant:

Ipgoal Microelectronics(sichuan) Co., Ltd, Sichuan, CN;

Inventor:

Ziche Zhang, Chengdu, CN;

Assignee:

IPGoa Microelectronics (Sichuan) Co., Ltd., Chengdu, Sichuan Province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

An interpolation circuit, includes a bias generating module, a load module consisting of a current source sub-module and a load resistance sub-module, first and second clock control modules, and an output module. The first clock control module includes a first input sub-module, a first source terminal negative feedback sub-module, a first multiplex switch sub-module and a first multiplex current sink sub-module. The bias generating module includes first, second and third FETs, and a bias current terminal. The current source sub-module includes fourth and fifth FETs. The load resistance sub-module includes first and second resistors. The first input sub-module includes sixth and seventh FETs. The first source terminal negative feedback sub-module includes a third resistor and a first capacitor. The first multiplex switch sub-module includes first and second groups of switches. The first multiplex current sink sub-module includes first and second groups of FETs. An interpolation system is further provided.


Find Patent Forward Citations

Loading…