The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8458637 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 04, 2013

Filed:

Oct. 22, 2010
Applicant:

Paul G. Curtis, Fort Collins, CO (US);

Inventor:

Paul G. Curtis, Fort Collins, CO (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, system, and computer program product are provided for implementing enhanced random logic macro (RLM) connectivity on a hierarchical design on an integrated circuit chip with top-level pipeline registers. Random logic macros (RLMs) to be connected are identified. Pipeline registers are identified; an input net is connected to an output net of the identified RLMs, removing the pipeline registers from the design. A chip floor plan results is displayed, providing direct RLM connectivity.


Find Patent Forward Citations

Curtis, Paul. (2013). Implementing enhanced rlm connectivity on a hierarchical design with top level pipeline registers (U.S. Patent No. 8458637). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8458637

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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