The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2013
Filed:
Apr. 21, 2010
Yoshihiro Ono, Tokyo, JP;
Takeshi Watanabe, Kanagawa, JP;
Naoshi Doi, Kanagawa, JP;
Itsuki Yamada, Kanagawa, JP;
Tsuneo Tsukagoshi, Tokyo, JP;
Yoshihiro Ono, Tokyo, JP;
Takeshi Watanabe, Kanagawa, JP;
Naoshi Doi, Kanagawa, JP;
Itsuki Yamada, Kanagawa, JP;
Tsuneo Tsukagoshi, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
A semiconductor integrated circuit design apparatus for analyzing a delay in a semiconductor integrated circuit. The semiconductor integrated circuit includes a delay analysis unit, a noise generation unit, a voltage fluctuation level analysis unit and a timing verification unit. The noise generation unit generates noise information based on a predetermined noise definition and the voltage fluctuation level analysis unit analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the generated noise information. Further, the timing verification unit makes the delay analysis unit analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis.