The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2013
Filed:
Aug. 03, 2011
Eric A. Foreman, Fairfax, VT (US);
James C. Gregerson, Hyde Park, NY (US);
Peter A. Habitz, Hinesburg, VT (US);
Jeffrey G. Hemmett, St. George, VT (US);
Debjit Sinha, Wappingers Falls, NY (US);
Natesan Venkateswaran, Hopewell Junction, NY (US);
Chandramouli Visweswariah, Croton-On-Hudson, NY (US);
Xiaoyue Wang, Kanata, CA;
Vladimer Zolotov, Putnam Valley, NY (US);
Eric A. Foreman, Fairfax, VT (US);
James C. Gregerson, Hyde Park, NY (US);
Peter A. Habitz, Hinesburg, VT (US);
Jeffrey G. Hemmett, St. George, VT (US);
Debjit Sinha, Wappingers Falls, NY (US);
Natesan Venkateswaran, Hopewell Junction, NY (US);
Chandramouli Visweswariah, Croton-On-Hudson, NY (US);
Xiaoyue Wang, Kanata, CA;
Vladimer Zolotov, Putnam Valley, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.