The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2013

Filed:

Dec. 17, 2010
Applicants:

Joseph G. Trotta, Plano, TX (US);

Noah Gottfried, Johnsonburg, NJ (US);

Richard Gammenthaler, McKinney, TX (US);

Inventors:

Joseph G. Trotta, Plano, TX (US);

Noah Gottfried, Johnsonburg, NJ (US);

Richard Gammenthaler, McKinney, TX (US);

Assignee:

Fujitsu Limited, Kawasaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 7/02 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0008 (2013.01); H04L 7/02 (2013.01); H04L 7/0331 (2013.01); H04L 7/0337 (2013.01); H04L 7/033 (2013.01);
Abstract

A system may include a bus carrying signals, a frame pulse generator generating a generally periodic frame pulse signal having timing boundaries delineating consecutive timing periods and a frame pulse enable signal active for a portion of each timing period proximate to the timing boundaries and inactive otherwise, a first controlled buffer driving the frame pulse signal on the bus during durations in which the frame pulse enable signal is active to generate a modified frame pulse, a reference clock controller receiving the modified frame pulse via the bus and generating a reference clock enable signal in response to presence of the modified frame pulse, a reference clock generator generating a generally periodic reference clock signal, and a second controlled buffer driving the reference clock signal on the bus during durations in which the reference clock enable signal is active to generate a modified reference clock.


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