The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2013

Filed:

May. 29, 2012
Applicant:

Daniel Liu, San Jose, CA (US);

Inventor:

Daniel Liu, San Jose, CA (US);

Assignee:

Headway Technologies, Inc., Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8239 (2006.01); G11C 5/08 (2006.01); G11C 11/15 (2006.01); H01L 21/8234 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 27/228 (2013.01); H01L 27/222 (2013.01);
Abstract

CMOS devices are provided in a substrate having a topmost metal layer comprising metal landing pads and metal connecting pads. A plurality of magnetic tunnel junction (MTJ) structures are provided over the CMOS devices and connected to the metal landing pads. The MTJ structures are covered with a dielectric layer that is polished until the MTJ structures are exposed. Openings are etched in the dielectric layer to the metal connecting pads. A seed layer is deposited over the dielectric layer and on inside walls and bottom of the openings. A copper layer is plated on the seed layer until the copper layer fills the openings. The copper layer is etched back and the seed layer is removed. Thereafter, an aluminum layer is deposited over the dielectric layer, contacting both the copper layer and the MTJ structures, and patterned to form a bit line.


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