The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2013
Filed:
Dec. 30, 2006
Andrew I. Russell, Plano, TX (US);
Gregory J. Hewlett, Richardson, TX (US);
Andrew I. Russell, Plano, TX (US);
Gregory J. Hewlett, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Disclosed embodiments utilize MIP techniques to determine optimum bit sequences that minimize PWM artifacts. The problem would first be restructured and redefined into a form suitable for MIP. An objective function designed to minimize PWM artifacts would allow for evaluation of resulting bit sequences in order to determine optimality. Constraints (that relate the inputs and variables) are developed. These constraints would determine whether a particular bit sequence can be used on a given system, and whether a particular bit sequence would satisfy any user defined rules. Once these are determined, an MIP solver would generate an optimized bit sequence(s). Only bit sequences that satisfy the constraints would be evaluated using the objective function, allowing for a quicker determination of a solution. This MIP solution may be generated quickly, allowing for a shorter production period while still optimizing the bit sequences to minimize PWM artifacts.