The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2013
Filed:
Aug. 07, 2008
Katsumi Matsumoto, Mobara, JP;
Kozo Yasuda, Mobara, JP;
Yasukazu Kimura, Chiba, JP;
Takuo Kaitoh, Mobara, JP;
Toshihiko Itoga, Chiba, JP;
Hiroshi Kageyama, Hachiouji, JP;
Katsumi Matsumoto, Mobara, JP;
Kozo Yasuda, Mobara, JP;
Yasukazu Kimura, Chiba, JP;
Takuo Kaitoh, Mobara, JP;
Toshihiko Itoga, Chiba, JP;
Hiroshi Kageyama, Hachiouji, JP;
Hitachi Displays, Ltd., Chiba-ken, JP;
Panasonic Liquid Crystal Display Co., Ltd., Hyogo-ken, JP;
Abstract
The gate electrode is formed above the polycrystalline semiconductor layer through the gate insulating film. The polycrystalline semiconductor layer includes a first region overlapping with the gate electrode in plan view. The first region is sandwiched between the second region and the third region. The second region of the polycrystalline semiconductor layer includes a first impurity diffusion region and two second impurity diffusion regions opposite in conductivity type to the first impurity diffusion region. The first region and the first impurity diffusion region are in contact with each other at a first boundary. The first region and the two second impurity diffusion regions are in contact with each other at second boundaries. The two second impurity diffusion regions sandwiching the first impurity diffusion region are provided along the gate electrode. Thus, a leak current is suppressed.