The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2013
Filed:
Nov. 04, 2011
Kook-joo Kim, Seongnam-si, KR;
Jin-ho Kim, Hwaseong-si, KR;
Seung-ki Chae, Seoul, KR;
Pil-kwon Jun, Seoul, KR;
Sun-hee Park, Hwaseong-si, KR;
Gyoung-eun Byun, Pyeongtaek-si, KR;
Kook-Joo Kim, Seongnam-si, KR;
Jin-Ho Kim, Hwaseong-si, KR;
Seung-Ki Chae, Seoul, KR;
Pil-Kwon Jun, Seoul, KR;
Sun-Hee Park, Hwaseong-si, KR;
Gyoung-Eun Byun, Pyeongtaek-si, KR;
Samsung Electronics Co., Ltd., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring.