The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2013
Filed:
Apr. 28, 2010
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Atsushi Iijima, Hong Kong, CN;
Tatsuya Harada, Tokyo, JP;
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Atsushi Iijima, Hong Kong, CN;
Tatsuya Harada, Tokyo, JP;
Headway Technologies, Inc., Milpitas, AZ (US);
SAE Magnetics (H.K.) Ltd., Hong Kong, CN;
TDK Corporation, Tokyo, JP;
Abstract
A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole.