The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2013
Filed:
Mar. 16, 2011
Applicants:
Robert C. Pack, Morgan Hill, CA (US);
William Wai Yan Ho, San Jose, CA (US);
Inventors:
Robert C. Pack, Morgan Hill, CA (US);
William Wai Yan Ho, San Jose, CA (US);
Assignee:
Worldwide Pro Ltd., Hong Kong, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
Technique assesses the impact of physical circuit variations, specification parameter variation, or process variations on clock, signal, and power network performance and through a hierarchical modeling and hierarchical Monte Carlo simulation method.
Quick Actions:
Pack, Robert. (2013). Hierarchical variation analysis of integrated circuits (U.S. Patent No. 8453102). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8453102
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile