The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2013

Filed:

Oct. 17, 2011
Applicants:

Myung-chul Kim, Austin, TX (US);

Natarajan Viswanathan, Austin, TX (US);

Samuel I. Ward, Austin, TX (US);

Inventors:

Myung-Chul Kim, Austin, TX (US);

Natarajan Viswanathan, Austin, TX (US);

Samuel I. Ward, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the datapath. The cells are placed using a wirelength optimization which assigns weights to wire sections based on the alignment direction. The rate of change of the alignment weighting value can vary during different stages of global placement. The invention is particularly suited for a force-directed placer which uses a linear system solver to obtain a globally optimum solution for placement of the cells having some overlap among the cells, and thereafter spreads the cells to reduce the overlap. Pseudo nets are also inserted which interconnect a cell and an expected location of the cell after spreading for that iteration.


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