Cryptographic processing using a processor

Abstract

In one embodiment, a cryptography processor compatible with the Advanced Encryption Standard (AES) for encrypting and decrypting has a memory storing each element of an AES State, normally 8-bit long, in a corresponding memory space that is at least 9 bits long. Using the larger memory spaces, the processor performs modified AES transformations on the State. A modified column-mixing transformation uses bit-shifting and XOR operations, thereby avoiding some multiplications and modulo reductions and resulting in some 9-bit State elements. A modified byte-substitution transformation uses a 512-element look-up table to accommodate 9-bit inputs. The modified byte-substitution transformation is combined with a modified row-shifting transformation. The memory has data registers each holding four State elements. A modified expanded key schedule is used in a modified round-key-adding transformation that is combined with the modified column-mixing transformation, wherein all four elements stored in a single data register are processed together in some operations.