The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8451667 B1

PDF
Full Text
Expired
Date of Patent:
May. 28, 2013

Filed:

Jan. 27, 2012
Applicants:

Jeffrey W Lutze, San Jose, CA (US);

Deepanshu Dutta, Santa Clara, CA (US);

Inventors:

Jeffrey W Lutze, San Jose, CA (US);

Deepanshu Dutta, Santa Clara, CA (US);

Assignee:

SanDisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.


Find Patent Forward Citations

Lutze, Jeffrey. (2013). Pair bit line programming to improve boost voltage clamping (U.S. Patent No. 8451667). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8451667

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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