Frame rate converter and display apparatus equipped therewith

Abstract

An input unit writes, into a memory unit, frames successively input from the outside. An interpolated frame generating unit reads multiple original frames from the memory unit, generates an interpolated frame between the original frames, and writes the interpolated frame into the memory unit. An output unit retrieves original frames and an interpolated frame from the memory unit and outputs to the outside the frames in the order in which the frames are to be displayed. The input unit, interpolated frame generating unit, and output unit operate in parallel to perform pipeline processing. Operation timing of each of the input unit and the interpolated frame generating unit is determined so that the timing at which the input unit writes an original frame into the memory unit differs from the timing at which the interpolated frame generating unit writes an interpolated frame into the memory unit.