The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2013
Filed:
Sep. 20, 2011
Uwe Fassnacht, Tuebingen, DE;
Veit Gernhoefer, Holzgerlingen, DE;
Michael S. Gray, Fairfax, VT (US);
Joachim Keinert, Altdorf, DE;
Uwe Fassnacht, Tuebingen, DE;
Veit Gernhoefer, Holzgerlingen, DE;
Michael S. Gray, Fairfax, VT (US);
Joachim Keinert, Altdorf, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.