The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2013
Filed:
Jun. 09, 2009
Stephen Kornachuk, San Jose, CA (US);
Carole Lambert, San Jose, CA (US);
James Mali, La Selva Beach, CA (US);
Brian Reed, San Jose, CA (US);
Scott T. Becker, Scotts Valley, CA (US);
Stephen Kornachuk, San Jose, CA (US);
Carole Lambert, San Jose, CA (US);
James Mali, La Selva Beach, CA (US);
Brian Reed, San Jose, CA (US);
Scott T. Becker, Scotts Valley, CA (US);
Tela Innovations, Inc., Los Gatos, CA (US);
Abstract
Within a dynamic array architecture, an irregular wire layout region within a portion of a chip level layout is bracketed by placing first and second regular wire layout shapes on a first and second sides, respectively, of the irregular wire layout region. One or more irregular wire layout shapes are placed within the irregular wire layout region. A first edge spacing is maintained between the first regular wire layout shape and a first outer irregular wire layout shape within the irregular wire layout region nearest to the first regular wire layout shape. A second edge spacing is maintained between the second regular wire layout shape and a second outer irregular wire layout shape within the irregular wire layout region nearest to the second regular wire layout shape. The first and second edge spacings are defined to optimize lithography of the regular and irregular wire layout shapes.