The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2013
Filed:
Dec. 24, 2010
Abhishek Kumar Tiwary, Uttar Pradesh, IN;
Anubhav Singh, Uttar Pradesh, IN;
Anuj Verma, New Delhi, IN;
Arnab Bhattacharya, Kolkata, IN;
Abhishek Kumar Tiwary, Uttar Pradesh, IN;
Anubhav Singh, Uttar Pradesh, IN;
Anuj Verma, New Delhi, IN;
Arnab Bhattacharya, Kolkata, IN;
Interra Systems Inc., Cupertino, CA (US);
Abstract
The invention discloses a method and a system for optimizing address generation for simultaneously running proximity-based Built-In-Self-Test (BIST) algorithms. The method also describes simultaneously testing proximity-based faults for different memories having column multiplexers of different sizes using the BIST algorithms. The system described above may be embodied in the form of a Built-In-Self-Test (BIST) controller. Further, the method includes selecting a memory having the largest size of column multiplexer (CM). After selecting the memory, size of an address-width register is extended to form an extended address-width register. Thereafter, an extended width address is generated using the extended address-width register and the extended width address is used to generate addresses for the memories. After generating the addresses, read and write operations are performed on the memories based on pre-defined rules, wherein the read and write operations provide testing of the memories.