The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2013
Filed:
Feb. 18, 2010
Anindya Saha, Bangalore, IN;
Manish Kumar, Nalanda, IN;
Hemant Mallapur, Bangalore, IN;
Santhosh Billava, Kundapur Taluk, IN;
Viji Rajangam, Thirunagar, IN;
Anindya Saha, Bangalore, IN;
Manish Kumar, Nalanda, IN;
Hemant Mallapur, Bangalore, IN;
Santhosh Billava, Kundapur Taluk, IN;
Viji Rajangam, Thirunagar, IN;
Saankhya Labs Pvt Ltd, Bangalore, IN;
Abstract
A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program Memory address to fetch an instruction packet. The program memory is closely coupled with the instruction buffer size to implement the zero overhead software pipelined (SFP) loop. The size of the zero overhead software pipelined (SFP) loop can exceed the instruction buffer size. A CPU control register includes a block count and an iteration count. The block count is loaded into a block counter and counts the plurality of instructions executed in the SFP loop, and the iteration count is loaded into an iteration counter and counts a number of iterations of the SFP loop based on the block count.