The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2013

Filed:

Mar. 12, 2007
Applicants:

Hiroyuki Furukawa, Iga, JP;

Kenichiroh Yamamoto, Chiba, JP;

Takashi Yoshii, Chiba, JP;

Masafumi Ueno, Ikoma, JP;

Yasuhiro Yoshida, Nara, JP;

Inventors:

Hiroyuki Furukawa, Iga, JP;

Kenichiroh Yamamoto, Chiba, JP;

Takashi Yoshii, Chiba, JP;

Masafumi Ueno, Ikoma, JP;

Yasuhiro Yoshida, Nara, JP;

Assignee:

Sharp Kabushiki Kaisha, Osaka-Shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 7/01 (2006.01);
U.S. Cl.
CPC ...
Abstract

It is an object to suppress a disturbance or distortion of an insertion image in the vicinity of an effective image edge portion such as an edge portion of a screen or the like caused by a moving compensation type frame rate conversion (FRC). An image processing device is provided with a moving vector detection circuit () for detecting a moving vector of an input image signal, an effective image edge portion judging circuit () for judging if a moving vector detecting position is adjacent to the effective image edge portion, and a vector switching circuit () for switching a vector in accordance with the judging result. The vector switching circuit () fixes the vector to 0 vector in the case where the moving vector detecting position is adjacent to the effective image edge portion. In the case where the position is in other region, the vector switching circuit () outputs the moving vector detected by the moving vector detection circuit () to an insertion vector allocation circuit ().


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