The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8446196 B1

PDF
Full Text
Expired
Date of Patent:
May. 21, 2013

Filed:

Jun. 10, 2010
Applicant:

Kazuo Watanabe, Kanagawa, JP;

Inventor:

Kazuo Watanabe, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

An input interface circuit according to the present invention includes an input first stage circuit that is connected to a signal terminal, where the signal terminal receives external data, and a phase adjustment circuit that adjusts an external input clock and a latch timing signal to be in phase, where the latch timing signal is output to latch circuits included in the input first stage circuit. The phase adjustment circuit adjusts delay time of the latch timing signal that passes through the clock tree circuit and is supplied to the latch circuit in response to a comparison result between the clock and an output from a replica delay circuit which is replicated from the clock.


Find Patent Forward Citations

Watanabe, Kazuo. (2013). Input interface circuit (U.S. Patent No. 8446196). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8446196

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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