The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2013

Filed:

Dec. 07, 2009
Applicants:

Jeremy D. Dunworth, San Diego, CA (US);

Gary J. Ballantyne, Christchurch, NZ;

Bhushan S. Asuri, San Diego, CA (US);

Jifeng Geng, San Diego, CA (US);

Gurkanwal S. Sahota, San Diego, CA (US);

Inventors:

Jeremy D. Dunworth, San Diego, CA (US);

Gary J. Ballantyne, Christchurch, NZ;

Bhushan S. Asuri, San Diego, CA (US);

Jifeng Geng, San Diego, CA (US);

Gurkanwal S. Sahota, San Diego, CA (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).


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