The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2013

Filed:

Jul. 16, 2009
Applicants:

Atsushi Himeno, Osaka, JP;

Takumi Mikawa, Shiga, JP;

Yoshio Kawashima, Osaka, JP;

Inventors:

Atsushi Himeno, Osaka, JP;

Takumi Mikawa, Shiga, JP;

Yoshio Kawashima, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided. A nonvolatile semiconductor memory device comprises a substrate; a plurality of stripe-shaped lower copper wires () formed on the substrate; an interlayer insulating layer () formed on the substrate provided with the lower copper wires (), a plurality of contact holes penetrating interlayer insulating layer () to surfaces of the lower copper wires (), respectively; electrode seed layers () and precious metal electrode layers () formed only at bottoms of the contact holes, respectively; resistance variable layers () filled into the contact holes such that the resistance variable layers are connected to the precious metal electrode layers (), respectively; a plurality of stripe-shaped upper copper wires () connected to the resistance variable layers (), respectively, and cross the lower copper wires (), respectively, and the electrode seed layers () and the precious metal electrode layers () are formed by selective growth plating.


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