The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2013
Filed:
Nov. 02, 2011
Jin-tae Noh, Suwon-si, KR;
Hun-hyeong Lim, Hwaseong-si, KR;
Ki-hyun Hwang, Seongnam-si, KR;
Jin-gyun Kim, Yongin-si, KR;
Sang-ryol Yang, Hwaseong-si, KR;
Jin-Tae Noh, Suwon-si, KR;
Hun-Hyeong Lim, Hwaseong-si, KR;
Ki-Hyun Hwang, Seongnam-si, KR;
Jin-Gyun Kim, Yongin-si, KR;
Sang-Ryol Yang, Hwaseong-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Abstract
In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.