The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2013
Filed:
Mar. 19, 2009
Philip N. Strenski, Yorktown Heights, NY (US);
Mark A. Lavin, Katonah, NY (US);
Philip N. Strenski, Yorktown Heights, NY (US);
Mark A. Lavin, Katonah, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for using layout enumeration to facilitate integrated circuit development includes defining an initial set of design ground rules represented in a notation compatible with a coarse placement grid, for a given layer(s) of an integrated circuit device; defining an initial region of interest for the integrated circuit device; enumerating, according to the initial set of design ground rules, each legal design layout for a given layer of the integrated circuit device in the initial region of interest; running a manufacturing simulation of the enumerated legal design layout data and, responsive to determining one or more failing layouts resulting therefrom, further determining whether the failing layouts may be eliminated by changes in technology parameters and/or updated ground rules. Upon eliminating the one or more failing layouts for the initial region of interest, expanding the initial region of interest and repeating the enumerating, manufacturing simulation, and triage assessment.