The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2013

Filed:

Dec. 15, 2010
Applicants:

Philip B. James-roxby, Longmont, CO (US);

Ralph D. Wittig, Menlo Park, CA (US);

Brendan K. Bridgford, Vienna, VA (US);

Robert M. Mcgee, Placitas, NM (US);

Richard Defelice, Pikesville, MD (US);

Inventors:

Philip B. James-Roxby, Longmont, CO (US);

Ralph D. Wittig, Menlo Park, CA (US);

Brendan K. Bridgford, Vienna, VA (US);

Robert M. McGee, Placitas, NM (US);

Richard DeFelice, Pikesville, MD (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution of an instruction by the first processor, the first processor suspends operation. In response to the first access transaction being a write transaction, the write transaction is not issued to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction. In response to the first access transaction being a read transaction, the read transaction is not issued to the peripheral device until the second processor executes the instruction.


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