The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2013
Filed:
Aug. 13, 2012
Aaron Nygren, San Francisco, CA (US);
Ming-ju Edward Lee, San Jose, CA (US);
Shadi Barakat, San Mateo, CA (US);
Xiaoling Xu, Cupertino, CA (US);
Toan Duc Pham, San Jose, CA (US);
Warren Fritz Kruger, Sunnyvale, CA (US);
Michael Litt, Toronto, CA;
Aaron Nygren, San Francisco, CA (US);
Ming-Ju Edward Lee, San Jose, CA (US);
Shadi Barakat, San Mateo, CA (US);
Xiaoling Xu, Cupertino, CA (US);
Toan Duc Pham, San Jose, CA (US);
Warren Fritz Kruger, Sunnyvale, CA (US);
Michael Litt, Toronto, CA;
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
ATI Technologies ULC, Markham, Ontario, CA;
Abstract
Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.