Capacitor mismatch error correction in pipeline analog-to-digital converters

Abstract

Various embodiments of methods and devices for reducing capacitor mismatch errors in a pipeline analog-to-digital converter (ADC) are disclosed. A plurality of pipeline element circuits are provided, where each pipeline element circuit corresponds to a given bit of the pipeline ADC. A first pipeline element circuit is configured to digitize analog A and B capacitor mismatch error calibration voltages generated by all the pipeline element circuits of the ADC when the pipeline ADC is operating in a capacitor mismatch calibration phase. According to one embodiment, digital representations corresponding to A and B capacitor mismatch error calibration voltages for each of the pipeline element circuits are provided to an output shift register and summing circuit, which generates capacitor mismatch error correction codes corresponding to each bit and pipeline element circuit. The capacitor mismatch error correction codes are applied to each bit weight of the pipeline ADC after conversion of analog signals input to the pipeline ADC has been completed.