The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2013
Filed:
Dec. 16, 2008
Koichiro Noguchi, Tokyo, JP;
Yoshio Kameda, Tokyo, JP;
Koichi Nose, Tokyo, JP;
Masayuki Mizuno, Tokyo, JP;
Toshinobu Ono, Kanagawa, JP;
Koichiro Noguchi, Tokyo, JP;
Yoshio Kameda, Tokyo, JP;
Koichi Nose, Tokyo, JP;
Masayuki Mizuno, Tokyo, JP;
Toshinobu Ono, Kanagawa, JP;
NEC Corporation, Tokyo, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (-) include: flip-flops () each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops () selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unitthat holds a set value and that provides the set value to first input terminal SI.