Memory devices including vertical pillars and methods of manufacturing and operating the same

Abstract

A semiconductor device includes a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are provided on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.