The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2013
Filed:
Sep. 17, 2009
Christy S. Tyberg, Mahopac, NY (US);
Katherine L. Saenger, Ossining, NY (US);
Jack O. Chu, Manhasset, NY (US);
Harold J. Hovel, Katonah, NY (US);
Robert L. Wisnieff, Ridgefield, CT (US);
Kerry Bernstein, Underhill, VT (US);
Stephen W. Bedell, Wappinger Falls, NY (US);
Christy S. Tyberg, Mahopac, NY (US);
Katherine L. Saenger, Ossining, NY (US);
Jack O. Chu, Manhasset, NY (US);
Harold J. Hovel, Katonah, NY (US);
Robert L. Wisnieff, Ridgefield, CT (US);
Kerry Bernstein, Underhill, VT (US);
Stephen W. Bedell, Wappinger Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.