The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2013

Filed:

Oct. 07, 2010
Applicants:

Kouichi Saitou, Ogaki, JP;

Yoshio Okayama, Gifu, JP;

Yoh Takano, Ogaki, JP;

Mayumi Nakasato, Ogaki, JP;

Inventors:

Kouichi Saitou, Ogaki, JP;

Yoshio Okayama, Gifu, JP;

Yoh Takano, Ogaki, JP;

Mayumi Nakasato, Ogaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H01L 21/82 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods for producing a substrate for mounting a device and for producing a semiconductor module are provided. The methods comprise preparing a metal plate on one major surface of which a plurality of projected electrodes are provided. An insulating resin layer is formed on the major surface so as to cover the top surface of the projected electrodes. The top surface of at least one of the plurality of projected electrodes is exposed by removing the insulating resin layer so that a major surface of the insulating resin layer opposite to the metal plate is level. A plurality of counter electrodes is arranged having a counterface to face the top face of the plurality of projected electrodes or a semiconductor device having a plurality of device electrodes is arranged to face the top face of the plurality of projected electrodes. The at least one of the plurality of projected electrodes, the top surface of which is exposed, is electrically connected with at least one of the plurality of counter electrodes facing the projected electrodes, by pressure-bonding the metal plate with the counter electrode. A wiring layer is formed by selectively removing the metal plate.


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