The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2013

Filed:

Sep. 28, 2007
Applicants:

Josephine Ammer Bolotski, Seattle, WA (US);

Jenny Bui, Seattle, WA (US);

Qi LU, Seattle, WA (US);

Inventors:

Josephine Ammer Bolotski, Seattle, WA (US);

Jenny Bui, Seattle, WA (US);

Qi Lu, Seattle, WA (US);

Assignee:

University of Washington, Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.


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