The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2013

Filed:

Nov. 19, 2010
Applicants:

Yi Zeng, Fremont, CA (US);

Freeman Zhong, San Ramon, CA (US);

Peter Windler, Fort Collins, CO (US);

Inventors:

Yi Zeng, Fremont, CA (US);

Freeman Zhong, San Ramon, CA (US);

Peter Windler, Fort Collins, CO (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.


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