Circuit driving for liquid crystal display device

Abstract

The present invention relates to a circuit for driving a liquid crystal display device in which no multi-flicker preventive signal FLK, but only single flicker preventive signal FLK, is used for reducing numbers of pins of a timing controller and a level shifter. The circuit for driving a liquid crystal display device includes a liquid crystal panel having a plurality of pixel regions for displaying an image, a timing controller for generating one flicker preventive signal and a plurality of clock signals and gate control signals to control driving timing of a gate driver, a gate pulse modulation unit for logically operating the one flicker preventive signal and the plurality of clock signals from the timing controller to generate a plurality of flicker preventive signals, and modulating a gate high voltage from the timing controller according to each of the plurality of flicker preventive signals generated thus to generate a plurality of modulated gate on voltages; a level shifter unit for changing the plurality of clock signals from the timing controller according to the plurality of modulated gate on voltages from the gate pulse modulation unit and a gate low voltage from the timing controller to generate a plurality of level shifted and modulated clock signals; and a gate driver for driving gate lines on the liquid crystal panel according to the a plurality of level shifted and modulated clock signals.