The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2013

Filed:

Apr. 06, 2011
Applicants:

Michael P. Chudzik, Danbury, CT (US);

Wiliam K. Henson, Beacon, NY (US);

Rashmi Jha, Wappingers Falls, NY (US);

Yue Liang, Beacon, NY (US);

Ravikumar Ramachandran, Pleasantville, NY (US);

Richard S. Wise, Newburgh, NY (US);

Inventors:

Michael P. Chudzik, Danbury, CT (US);

Wiliam K. Henson, Beacon, NY (US);

Rashmi Jha, Wappingers Falls, NY (US);

Yue Liang, Beacon, NY (US);

Ravikumar Ramachandran, Pleasantville, NY (US);

Richard S. Wise, Newburgh, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.


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