The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2013

Filed:

Dec. 14, 2010
Applicants:

David Samuel Goldman, Thornhill, CA;

Bruce B. Pedersen, Sunnyvale, CA (US);

Gabriel Quan, Toronto, CA;

Yuen Ho Choi, Markham, CA;

Inventors:

David Samuel Goldman, Thornhill, CA;

Bruce B. Pedersen, Sunnyvale, CA (US);

Gabriel Quan, Toronto, CA;

Yuen Ho Choi, Markham, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 13/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable chip design tool is provided to enumerate and specify the security and/or redundancy constraints of a programmable chip design. A design is implemented with a high-level security or redundancy scheme, and the programmable chip design tool applies the scheme while simultaneously optimizing for desired metrics (logic density, routability, timing, power, etc.). An underlying assignment scheme as well as user interface components used to enter this assignment scheme are provided.


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