The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2013

Filed:

Dec. 26, 2008
Applicant:

Ryoji Ishikawa, Kanagawa, JP;

Inventor:

Ryoji Ishikawa, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In order to improve a failure detection rate in a layout automatic design process of a DFT circuit, signal lines of the DFT circuit are aggregated by an AND tree circuitor an OR tree circuit instead of an EXOR tree circuit, and outputs thereof are received by an observation flip-flop. When a failure detection process of the DFT circuit is performed by using the EXOR tree circuit in the case where partial circuits outputting respective signal lines are shared or the partial circuits have the same structure, the signals cancel each other and the failures of the original partial circuits cannot be detected in some cases. However, such a trouble can be prevented by using the AND tree circuitor the OR tree circuit instead of the EXOR tree circuit.


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