The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2013
Filed:
Aug. 16, 2007
Leo James Clark, Kerrville, TX (US);
James Stephen Fields, Jr., Austin, TX (US);
Guy Lynn Guthrie, Austin, TX (US);
William John Starke, Round Rock, TX (US);
Derek Edward Williams, Austin, TX (US);
Phillip G. Williams, Leander, TX (US);
Leo James Clark, Kerrville, TX (US);
James Stephen Fields, Jr., Austin, TX (US);
Guy Lynn Guthrie, Austin, TX (US);
William John Starke, Round Rock, TX (US);
Derek Edward Williams, Austin, TX (US);
Phillip G. Williams, Leander, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.