The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2013

Filed:

Aug. 31, 2009
Applicants:

Matthew Phillip Ferringer, Round Hill, VA (US);

Ronald Scott Clifton, Leesburg, VA (US);

Timothy Guy Thompson, Purcellville, VA (US);

Inventors:

Matthew Phillip Ferringer, Round Hill, VA (US);

Ronald Scott Clifton, Leesburg, VA (US);

Timothy Guy Thompson, Purcellville, VA (US);

Assignee:

The Aerospace Corporation, El Segundo, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 15/18 (2006.01); G06F 15/00 (2006.01); G06F 15/76 (2006.01); G06F 15/16 (2006.01); G06N 3/00 (2006.01); G06N 3/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods are provided for a core management system for parallel processing of an evolutionary algorithm. The systems and methods may include identifying, for a processing environment, a plurality of arriving processors available for utilization; configuring a first number of the plurality of arriving processors as master processors for the processing environment; configuring a respective second number of the plurality of arriving processors as slave processors, where each master processor is assigned one or more of the slave processors for the processing environment, where each master processor maintains timing data associated with available processing resources at the respective master processor, where each master processor is operative to calculate a respective target number of slaves based upon the respective timing data; and reconfiguring a current number of slave processors assigned to one or more respective master processors based upon the respective timing data calculated for the one or more respective master processors.


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