The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2013
Filed:
Aug. 06, 2009
Kazuya Matsumoto, Kyoto, JP;
Yasuyuki Doi, Kyoto, JP;
Kazuya Matsumoto, Kyoto, JP;
Yasuyuki Doi, Kyoto, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A data signal loading circuit (i) which includes: a comparator CMPreceiving clock signal CKP and reverse-phase signal CKN of clock signal CKP, and outputting clock signal CLPwhich is in phase with clock signal CKP, and clock signal CLNhaving a reverse phase of clock signal CKP; a comparator CMPhaving a non-inverting input terminal receiving clock signal CLP, and an inverting input terminal receiving clock signal CLN; and a comparator CMPhaving an inverting input terminal receiving clock signal CLP, and a non-inverting input terminal receiving clock signal CLN, and (ii) which, by using output signals CLand CLof the comparator CMPand the comparator CMPas clock signals for latch circuits Land L, equalizes delay times for the rise or fall of clock signals CLand CLinputted to the latch circuits Land L, and (iii) has low power consumption.