The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2013

Filed:

Oct. 12, 2011
Applicants:

Yoshitaka Dozen, Tochigi, JP;

Tomoyuki Aoki, Tochigi, JP;

Hidekazu Takahashi, Tochigi, JP;

Daiki Yamada, Tochigi, JP;

Eiji Sugiyama, Tochigi, JP;

Kaori Ogita, Tochigi, JP;

Naoto Kusumoto, Isehara, JP;

Inventors:

Yoshitaka Dozen, Tochigi, JP;

Tomoyuki Aoki, Tochigi, JP;

Hidekazu Takahashi, Tochigi, JP;

Daiki Yamada, Tochigi, JP;

Eiji Sugiyama, Tochigi, JP;

Kaori Ogita, Tochigi, JP;

Naoto Kusumoto, Isehara, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.


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