The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2013

Filed:

Feb. 25, 2011
Applicants:

Kwangmin Park, Seoul, KR;

Juwan Lim, Hwaseong-si, KR;

Seungjae Baik, Hwaseong-si, KR;

Siyoung Choi, Seongnam-si, KR;

Kihyun Hwang, Seongnam-si, KR;

Juyul Lee, Seoul, KR;

Inventors:

Kwangmin Park, Seoul, KR;

Juwan Lim, Hwaseong-si, KR;

Seungjae Baik, Hwaseong-si, KR;

Siyoung Choi, Seongnam-si, KR;

Kihyun Hwang, Seongnam-si, KR;

Juyul Lee, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract

A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the gate electrode and the substrate, the charge trapping layer having trap sites configured to trap charges; a charge tunneling layer between the trapping layer and the semiconductor substrate; and a charge blocking layer between the gate electrode and the trapping layer. The charge trapping layer comprises a deep trapping layer having a plurality of energy barriers and a high density trapping layer having a trap site density higher than a trap site density of the deep trapping layer.


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