The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2013

Filed:

Jan. 12, 2012
Applicants:

Takuji Matsumoto, Kanagawa, JP;

Tetsuji Yamaguchi, Kanagawa, JP;

Keiji Tatani, Kanagawa, JP;

Yutaka Nishimura, Kanagawa, JP;

Kazuichiro Itonaga, Tokyo, JP;

Hiroyuki Mori, Kanagawa, JP;

Norihiro Kubo, Kanagawa, JP;

Fumihiko Koga, Kanagawa, JP;

Shinichiro Izawa, Kanagawa, JP;

Susumu Ooki, Kanagawa, JP;

Inventors:

Takuji Matsumoto, Kanagawa, JP;

Tetsuji Yamaguchi, Kanagawa, JP;

Keiji Tatani, Kanagawa, JP;

Yutaka Nishimura, Kanagawa, JP;

Kazuichiro Itonaga, Tokyo, JP;

Hiroyuki Mori, Kanagawa, JP;

Norihiro Kubo, Kanagawa, JP;

Fumihiko Koga, Kanagawa, JP;

Shinichiro Izawa, Kanagawa, JP;

Susumu Ooki, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A solid-state imaging device includes a semiconductor substrate including a pixel portion having a photoelectric conversion portion and a peripheral circuit portion; a first sidewall composed of a sidewall film and disposed on each sidewall of gate electrodes of MOS transistors in the pixel portion; a second sidewall composed of the sidewall film and disposed on each sidewall of gate electrodes of MOS transistors in the peripheral circuit portion; a first silicide blocking film composed of the sidewall film and disposed on the photoelectric conversion portion and a part of the MOS transistors in the pixel portion; and a second silicide blocking film disposed on the MOS transistors in the pixel portion so as to overlap with a part of the first silicide blocking film, wherein the MOS transistors in the pixel portion are covered with the first and second silicide blocking films.


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