The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2013
Filed:
Jun. 18, 2010
Applicant:
Petar Grbovic, Vernon, FR;
Inventor:
Petar Grbovic, Vernon, FR;
Assignee:
Schneider Toshiba Inverter Europe SAS, Pacy sur Eure, FR;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
Abstract
The invention relates to a gate control device for a JFET-type transistor that has a gate, a drain and a source. The gate control device includes a voltage generation circuit comprising an output connected to the gate of the transistor, where the circuit is designed to generate at the output a reference gate-source voltage following a predetermined voltage ramp. A voltage limiting circuit is designed to limit the reference gate-source voltage to a predetermined maximum value when the gate-source voltage at the terminals of the JFET transistor has reached said maximum value.