Clock generation circuit and delay locked loop using the same

Abstract

A clock generation circuit includes a plurality of variable delay units configured to control a delay of an input clock signal under the control of delay control signals assigned thereto among a plurality of delay control signals, and output a plurality of delayed clock signals; a phase comparison unit configured to compare a phase of a reference clock signal which has a predetermined phase difference from the input clock signal and a phase of a delayed clock signal which is outputted from any one variable delay unit among the plurality of variable delay units; and a delay control unit configured to generate the plurality of delay control signals based on a comparison result from the phase comparison unit.