The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2013

Filed:

Aug. 06, 2012
Applicants:

Teppei Iwase, Hyogo, JP;

Yoshihiro Tomura, Osaka, JP;

Kazuhiro Nobori, Osaka, JP;

Yuichiro Yamada, Osaka, JP;

Kentaro Kumazawa, Osaka, JP;

Inventors:

Teppei Iwase, Hyogo, JP;

Yoshihiro Tomura, Osaka, JP;

Kazuhiro Nobori, Osaka, JP;

Yuichiro Yamada, Osaka, JP;

Kentaro Kumazawa, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.


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