The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Aug. 08, 2011
Fook-luen Heng, Yorktown Heights, NY (US);
Rajiv V. Joshi, Yorktown Heights, NY (US);
Alexey Y. Lvov, Congers, NY (US);
Xiaoping Tang, Mohegan Lake, NY (US);
Fook-Luen Heng, Yorktown Heights, NY (US);
Rajiv V. Joshi, Yorktown Heights, NY (US);
Alexey Y. Lvov, Congers, NY (US);
Xiaoping Tang, Mohegan Lake, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.