The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8423715 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 16, 2013

Filed:

May. 01, 2008
Applicants:

Timothy H. Heil, Rochester, MN (US);

Robert A. Shearer, Rochester, MN (US);

Inventors:

Timothy H. Heil, Rochester, MN (US);

Robert A. Shearer, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory hierarchy in a computer includes levels of cache. The computer also includes a processor operatively coupled through two or more levels of cache to a main random access memory. Caches closer to the processor in the hierarchy are characterized as higher in the hierarchy. Memory management among the levels of cache includes identifying a line in a first cache that is preferably retained in the first cache, where the first cache is backed up by at least one cache lower in the memory hierarchy and the lower cache implements an LRU-type cache line replacement policy. Memory management also includes updating LRU information for the lower cache to indicate that the line has been recently accessed.


Find Patent Forward Citations

Heil, Timothy. (2013). Memory management among levels of cache in a memory hierarchy (U.S. Patent No. 8423715). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8423715

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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